Wide bandgap semiconductor innovation has outperformed conventional silicon-based semiconductors in the electronic instrument business in terms of profitability and efficiency. One of the most technologically sophisticated semiconductors is wide bandgap silicon carbide (SiC), which has substantial importance.These semiconductors perform well in a variety of applications, including high temperature, frequency, voltage, etc.
Silicon carbide (SiC) has superior electrical properties which are used to fabricate next-generation devices, along with well-developed manufacturing methods. The SiC JFET’s fast switching speed and low on-state resistance are enticing the market. This makes it a highly sought-after component in the expanding commercial electronics sector. It has the high input impedance to permit high degree of isolation between input-output circuit.
A group of researchers from the Tunisia’s University of Monastir and France’s Université de Lyon created a multidimensional JFET structure to improve performance and validate it through testing on the model [1] already presented in the paper “A multi-physics model of the VJFET with a lateral channel” [2].
JFET layout and characteristics
JFETs consist of lateral and vertical channels in series connection and are unipolar devices. SiCED/INFINEON (TO220 package) manufactures the 1200V SiC JFET, which has a die size of 2.4×2.4mm 2, an on-resistance of 300m, a threshold gate voltage of -20V, and a saturation current of 20A.
We can observe three physical capacitances between gate and source (CjGS), gate and point M (CjGM), and drain and source (CjDS) in the static and dynamic JFET circuit models, with an extra capacitor between the drain and point M. (C jMD ). In comparison, the capacitors used in the circuit have a much higher impedance level.
As capacitors have low resistance, the resultant circuit model in figure 3 clearly illustrates that the capacitors will only alter the characteristics.
CGS, CDS, and CGD are calculated by adding the total capacitance between each terminal of the JFET. [Note: Because two capacitors are connected in series between the gate and drain, they are calculated using the formula for the resultant (total) capacitance between the two sites.
CGS = C JGS
CDS = CjDS
1/CGD = 1/C jGM + 1/CjMD
Numeric simulation performed
The researchers chose ISE TCAT Software for 2D numerical simulation of the SiC-JFET, which is provided in the study publication.
To begin the simulation, a negative gate bias of -20 V is provided to ensure that the JFET is in the off state. When the lateral channel is totally blocked, the capacitances may be recovered in numerical simulations using a tiny AC signal analysis overlaid on the DC bias voltage.
The graph below compares observed CDS (VDS), CGD (VGD), CGS (VDS), and CGS (VGS) to those produced from 2D numerical simulations and an analytical model.
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Results after numerical simulation performed
After running the numerical simulation, the findings and measurements of the capacitances CGD, CGS, and CDS are analyzed, and the capacitance values are connected to the corresponding space charge (SCR) width. The following criteria will be utilized to calculate the SCR border.
In the following equation, (x) represents net doping concentrations, p(x,t) signifies net hole concentrations, and n(x,t) indicates electron concentrations, where x and t comprise spatial and time variables, respectively.
The simulated graphs show the measured, numerically simulated, and analytical models of planar junction gate-source CGS and CDS capacitances vs VDS, respectively. According to the equations for the CDS model, CGS (shown as a circle and top arrow with about 400pF capacitance) weakly rises with VDS, while CGS is dependent on V GS and is similar to a gate-source planar capacitance. The researchers notice that the experimental and simulation results correspond in this situation, which is not the case in the third example of CDS and CGS capacitance, where the CGD capacitance does not fit with a planar junction capacitance. To address this disparity, the researchers provided an analytical model of the CGD capacitance based on TCAD numerical analysis.
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It can possibly be confirmed that a relationship exists between the CGD measured capacitance and that estimated using the analytical model.
SiC JFET Dynamic Model Validation
Validation of the suggested approach is critical for each experiment. To achieve this, the team conducts studies to assess the validity of dynamic performances in switching conditions. The inductive switching simulation circuit contains a load resistance R, a load inductance L, and a gate resistance RG.
A comparison of simulated (blue waveforms) and actual (green waveforms) findings for inductive-resistive switching turn-off shows that both are in good agreement. The places at which two waveforms coincide are ideal; but, in practice, there will be some difference in inaccuracy. The goal is to minimize errors in order to get optimal results.
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Conclusion
The study paper is based on the work done in [2], which aimed to enhance and validate the JFET’s multidimensional structure. Under blocking circumstances of static and dynamic circuit models of the JFET, capacitors were linked in series and parallel between each terminal. The numerical simulation for C-V characteristics produced varying results, with a few findings deviating from the pattern established by others. The team established a dynamic model for the vertical SiC JFET with the lateral channel that accounts for the multi-function impact in terminal capacitance in this [1] research article. The dynamic model was then run in VHDL-AMS software, and the simulation results were confirmed against experimental data under inductive-resistive switching circumstances and capacitance-voltage measurement.
Fourth International Conference on Engineering & MIS 2018 published the study report under closed access.
References
[1] M. Hervé et al., " A multi-physics model of the VJFET with a lateral channel," Proceedings of the 2011 14th European Conference on Power Electronics and Applications, 2011, pp. 1-10.
[2] Sami Ghedira, Hervé Morel, and Kamel Besbes. 2018. Dynamic Circuit Model of SiC VJFET For Power Integrated Circuit Design. In Proceedings of the Fourth International Conference on Engineering; MIS 2018 (ICEMIS '18). Association for Computing Machinery, New York, NY, USA, Article 48, 1–6. DOI:https://doi.org/10.1145/3234698.3234746
